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| US3881 CMOS Low Voltage Hall Effect Latch Features and Benefits * * * * * Chopper stabilized amplifier stage Optimized for BDC motor applications New miniature package / thin, high reliability package Operation down to 2.2V CMOS for optimum stability, quality, and cost Applications * * * * * * Solid state switch Brushless DC motor commutation Speed sensing Linear position sensing Angular position sensing Current sensing Ordering Information Part No. US3881 US3881 Temperature Suffix Package Temperature Range E SO or UA -40oC to 85oC Commercial L SO or UA -40oC to 150oC Automotive * Contact factory or Sale Representative for legacy temperature options Functional Diagram Description The US3881 is a bipolar Hall effect sensor IC fabricated from mixed signal CMOS technology. It incorporates advanced chopper stabilization techniques to provide accurate and stable magnetic switch points. There are many applications for this sensor in addition to those listed above. The design, specifications, and performance have been optimized for commutation applications in 5V and 12V brushless DC motors. The output transistor will be latched on (BOP) in the presence of a sufficiently strong South pole magnetic field facing the marked side of the package. Similarly, the output will be latched off (BRP) in the presence of a North field. SO Package Pin 1 - VDD Pin 2 - Output Pin 3 - GND V DD Output Voltage Regulator Chopper GND UA Package Pin 1 - VDD Pin 2 - GND Pin 3 - Output The SOT-23 device is reversed from the UA package. The SOT-23 output transistor will be latched on in the presence of a sufficiently strong North pole magnetic field subjected to the marked face. Note: Static sensitive device; please observe ESD precautions. Re verse VDD protection is not included. For reverse voltage protec tion, a 100 resistor in series with VDD is recommended. US3881 CMOS Low Voltage Hall Effect Latch 3901003881 Rev 4.2 7/23/01 Page 1 US3881 CMOS Low Voltage Hall Effect Latch US3881 Electrical Specifications DC Operating Parameters: TA = 25, VDD = 12VDC (unless otherwise specified). Parameter Supply Voltage Supply Current Saturation Voltage Output Leakage Output Rise Time Output Fall Time Symbol Test Conditions VDD Operating IDD VDS(on) IOFF tr tf B DC Operating Parameters: TA = -40 to 150oC, VDD =12 VDC (unless otherwise specified). 1mT=10 Gauss. Parameter Operating Point Release Point Hysteresis Symbol Test Conditions BOP BRP Bhys Min 1.0 -9.0 5.5 Typ 5.0 -5.0 10.0 Max 9.0 -1.0 12.0 Units mT mT mT Absolute Maximum Ratings Supply Voltage (Operating), VDD Supply Current (Fault), IDD Output Voltage, VOUT Output Current (Fault), IOUT Power Dissipation, PD Operating Temperature Range, T A Storage Temperature Range, T S Maximum Junction Temp, TJ ESD Sensitivity (All Pins) 18V 50mA 18V 50mA 100mW -40 to 150C -65 to 150C 175C +/- 4KV Melexis Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function o r design. Melexis does not assume any liability arising from the use of any product or application of any product or circuit described herein. US3881 CMOS Low Voltage Hall Effect Latch 3901003881 Rev 4.2 7/23/01 Page 2 US3881 CMOS Low Voltage Hall Effect Latch Performance Graphs Typical Magnetic Switch Points versus Supply Voltage 12.5 Typical Magnetic Switch Points versus Temperature 12.5 3881 3881 B HYS 7.5 B OP 2.5 7.5 Flux Density (mT) Flux Density (mT) B OP 2.5 -2.5 B RP -7.5 -2.5 B RP -7.5 -12.5 0 5 10 15 20 25 30 -12.5 -40 0 40 80 120 160 200 Supply Voltage (V) Temperature (oC) Min/Max Magnetic Switch Range versus Temperature 12.5 Output Voltage versus Flux Density 25 3881 3881 7.5 B Max OP 20 V DD B OP Flux Density (mT) Output Voltage (V) 2.5 B Min OP 15 B RP 10 -2.5 B P Max R -7.5 5 B P Min R V out -12.5 -40 0 0 40 80 120 160 200 -30 -20 -10 0 1 0 2 0 30 Temperature (oC) Flux Density (mT) US3881 CMOS Low Voltage Hall Effect Latch 3901003881 Rev 4.2 7/23/01 Page 3 US3881 CMOS Low Voltage Hall Effect Latch Performance Graphs Performance Graphs Typical Supply Current versus Supply Voltage 5 Typical Saturation Voltage versus Temperature VDD = 12 V, IOUT = 20mA 3881 500 3881 4 TA = -40oC 400 V DS(ON) Supply Current (mA) V DS(ON) (mV) 3 TA = 25 oC 300 2 TA = 125 oC 200 1 100 0 0 5 10 15 20 25 30 0 -40 0 40 80 120 160 200 Supply Voltage (V) Temperature (oC) Power Dissipation versus Temperature 500 Wave Soldering Parameters All Devices All Devices 280 Package Power Dissipation (mW) 400 UAPackage R J A =206o C/W 300 o Solder Temperature ( C) 260 240 200 220 100 SOPackage R J A =575o C/W 0 -40 200 0 40 80 120 160 200 0 5 10 15 20 25 30 Temperature (oC) Time in Wave Solder (Seconds) 3901003881 Rev 4.2 7/23/01 Page 4 US3881 CMOS Low Voltage Hall Effect Latch US3881 CMOS Low Voltage Hall Effect Latch Unique Features CMOS Hall IC Technology The chopper stabilized amplifier uses switched capacitor techniques to eliminate the amplifier offset voltage, which, in bipolar devices, is a major source of temperature sensitive drift. CMOS makes this advanced technique possible. The CMOS chip is also much smaller than a bipolar chip, allowing very sophisticated circuitry to be placed in less space. The small chip size also contributes to lower physical stress and less power consumption. Applications If reverse supply protection is desired, use a resistor in series with the VDD pin. The resistor will limit the Supply Current (Fault), IDD, to 50 mA. For severe EMC conditions, use the application circuit below. Installation Consider temperature coefficients of Hall IC and magnetics, as well as air gap life time variations. Observe temperature limits during wave soldering. Applications Examples Automotive and Severe Environment Protection Circuit R1 100 VDD D1 Z1 C1 Supply Voltage 4.7nF Two Wire Optional Current Biasing Circuit RL IDD V RL 1.2K OUT C2 4.7nF DD IIN Iout Hall IC VSS Rb Hall IC The resistors Rb and RL can be used to bias the input current, Iin. Refer to the part specification for limiting values. This circuit will help in getting the precise ON and OFF currents desired. B RP = Ioff = (VDD / Rb + IDD ) B OP = Ion = (Ioff + VDD / RL ) US3881 CMOS Low Voltage Hall Effect Latch 3901003881 Rev 4.2 7/23/01 Page 5 US3881 CMOS Low Voltage Hall Effect Latch Physical Characteristics 1.60 1.40 4.30 3.90 2.64 2.34 45o Typical UA Package Dimensions 5o Typical UA Hall Plate / Chip Location 2.13 1.87 0.45 0.41 0.84 0.63 1.53 1.27 U38 * 104 0.48 0.43 3.20 2.80 45o Typical Marked Surface All Dimensions in millimeters 1.75 1.55 0.38 Typical (see note 3) 0.20 0.00 0.41 0.35 1 2 3 NOTES: 1.) Controlling dimension: mm 2.) Leads must be free of flash and plating voids 3.) Do not bend leads within 1mm of the lead to package interface. 4.) Package dimensions exclude molding flash 5.) Tolerance is 0.254mm unless otherwise specified 15.5 14.5 * MARKING: Line 1: 1st digit (U) 2nd and 3rd digits (38) Line 2: 1st digit (1) 2nd and 3rd digits(04) = Supplier (Melexis) = Series (3880) = Year (2001) = Week of Year 1.30 1.24 PINOUT: Pin 1 Pin 2 Pin 3 2.57 2.51 0.41 0.35 V DD GND Output SOT-23 Package Dimensions (Top View) 0.50 0.35 0.20 MIN 3 3.00 2.60 3104 1 2.10 1.70 * 2 1.80 1.50 chip 0.66 0.56 0.25 0.10 Pin # 3.10 2.70 0.10 0.00 NOTES: 1. MARKING: 1st Digit (3) = Series (3881) 2nd Digit(1) = Year - 2001 Last Digits (04) = Week of Year 2. PINOUT (See Top View at left): Pin 1 VDD Pin 2 Output Pin 3 GND 3. Controlling dimension: mm. 4. Lead thickness after solder plating will be 0.254 mm maximum. 5. Package dimensions exclude molding flash. 6. The end flash shall not exceed 0.127 mm on each side of package. 7. Tolerance is +/- 0.254 mm unless otherwise specified. SOT-23 Hall Plate / Chip Location (Bottom View) 0.95 0.85 0.90 0.70 1.30 1.00 1.55 1.45 For the latest version of this document, Go to our website at: WWW.melexis.com Or for additional information Contact Melexis Direct: Europe and Japan E-mail: sales_europe@melexis.com Phone: 011-32-13-670-780 US3881 CMOS Low Voltage Hall Effect Latch USA and rest of the world E-mail: sales_usa@melexis.com Phone: (603)-223-2362 3901003881 Rev 4.2 7/23/01 Page 6 |
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